(1) Field of the Invention
The present invention relates to an information regenerating apparatus wherein recorded data constructed of a sector mark and a following header section having a plurality of data sets each having a pull-in pattern, an address mark and address information, is read out to form a regenerative signal which in turn is used to regenerate information.
(2) Description of the Prior Art
An optical disc system is known as one of image regenerating apparatuses which trace tracks formed on a recording medium and thereby read out data recorded on tracks. In the system, after predetermined signal processing is performed, the data recorded on tracks is regenerated by using a clock signal that is produced in correspondence with the readout speed of the data recorded using a phase-locked loop circuit (to be abbreviated as a PLL circuit hereinafter). In the system, this PLL circuit is constructed so as to be able to operate at two levels of response speeds, so that the clock signal to be produced may be pulled in quickly to the frequency of the input signal while influences of noises etc. are reduced after the completion of the pull-in operation.
That is, in performing phase-synchronization with respect to a pull-in pattern (to be referred to hereinafter as a VFO pattern), the PLL circuit effects phase-synchronization at a fast response speed. On the other hand, when the circuit detects a pattern "100" in the VFO pattern at a predetermined number of times, the circuit judges that the pull-in process is over and changes the response speed of phase-synchronization to a slow level.
Nevertheless, if the regenerative signal is deteriorated or if there are defects, even fine ones on the recording medium, it becomes impossible for the circuit to perform the successive detection of the pattern "100" contained in the VFO pattern so that the number of detection of the pattern could not reach the predetermined number. When such a failure occurs in the above configuration, the PLL circuit happens to perform phase-synchronization at the fast response speed for bit strings of address information or user information coming next to the VFO pattern. In this case, if the regenerative signal contains defects due to failures of the recording medium or any other reason, the PLL circuit tends to follow or pick up the defects because of the fast response speed. Consequently, the state of synchronization tends to become unstable so that there is a fear that burst errors take place.
In order to solve this problem, a method has been proposed in Japanese Patent Application Laid-Open Hei 4 No. 162,263. This prior art method will now be described with reference to FIG. 1.
In the configuration according to the prior art, a mono-stable multi-vibrator 96 for measuring a time substantially equal to a pickup duration for the VFO pattern is provided as a signal generator of producing a signal for switching the response speed of a PLL circuit 95. A read gate signal 91 instructing a start of pickup is inputted to the mono-stable multi-vibrator 96. A latch 97 reads the data of a regenerative signal 92 in synchronization with a clock signal produced in the PLL circuit 95 and sends out the picked up data as an output 94.
In the above configuration, when the read gate signal 91 instructs the PLL circuit 95 to start the operation, the mono-stable multi-vibrator 96 starts measurement. Here, the operation start of the PLL circuit 95 is instructed by controlling a switch 98 so that the signal to be supplied to the PLL circuit 95 is changed over from a reference clock 93 to a regenerative signal 92. As a result, the PLL circuit 95 performs phase-synchronization for the VFO pattern at a fast response speed in the beginning of the operation, and when the mono-stable multi-vibrator 96 has completed the measurement of a predetermined time, the circuit 95 performs phase-synchronization at a slow response speed.
In other words, the PLL circuit 95 performs fast response speed phase-synchronization for VFO patterns and at the time of picking up the data in image information area the circuit 95 starts to effect slow response speed phase-synchronization even if a predetermined length of the VFO pattern was not detected due to defects in the recording medium or any other reason.
The above-stated conventional configuration, however, suffers the following problems, especially in the case where data recorded on a recording medium is constructed in such a manner as designated by a reference numeral 57 in FIG. 4 hereinbelow, that a sector mark 571 is followed by a header section 572 to 575 which contains plural data sets each consisting of a VFO pattern 572, an address mark 573 and address information 574.
That is, it is possible for the PLL circuit 95 to perform fast response speed phase-synchronization for a first VFO pattern 572a following the sector mark 571, but the PLL circuit 95 effects phase-synchronization for subsequently appearing VFO patterns 572 at a slow response speed. Therefore, it takes long time to finish the phase-synchronization, and the phase-synchronization for the VFO pattern cannot be completed during the duration for picking up VFO patterns 572, thereby resulting in incapacity for picking up the following address information 574.
Further, there is another problem. That is, as the PLL circuit 95 can effect fast response speed phase-synchronization at the start of operation until the monostable multi-vibrator 96 completes the measurement of the predetermined time, the circuit 95 continues to stay in the fast phase-synchronization mode even after the completion of the phase-synchronization. Therefore, if the regenerative signal contains any fine defect in this duration, the PLL circuit 95 tends to become unstable.